1. Field of the Invention
The present invention relates to a frequency dividing circuit, and more particularly, to a variable frequency dividing circuit which is capable of dividing a frequency by a non-integer and adjusting a frequency division ratio as desired.
2. Discussion of Related Art
Generally, a frequency dividing circuit, which counts an oscillation clock and outputs the frequency-divided clock, is widely used in a frequency generator for appropriately dividing a basic oscillation frequency to generate a desired frequency. However, a conventional frequency dividing circuit has various problems. First, construction of the conventional circuit is complicated. Second, in response to an input frequency increasing and decreasing control signals are generated after a long delay. Third, a delay time period is increased before generation of frequency variation. Finally, the conventional circuit is easily influenced by noise.
FIG. 1 is a block diagram illustrating a conventional variable frequency dividing circuit. FIG. 2 is a circuit diagram illustrating a variable controller 20 of FIG. 1, and FIG. 3 is a circuit diagram illustrating a frequency divider 40 of FIG. 1.
As shown in FIG. 1, the conventional variable frequency dividing circuit includes a variable controller 20, which receives as inputs a frequency increasing signal INCMT, a frequency decreasing signal DECMT, a clock pulse CP, and a reset sinal RST to output an increasing control signal IN.sub.-- INC and a decreasing control signal IN.sub.-- DEC. The conventional circuit also includes a frequency divider 40, which receives the increasing control signal IN.sub.-- INC and the decreasing control signal IN.sub.-- DEC from the variable controller 20, and performs a frequency division.
Under the above construction, if a frequency higher or lower than a current frequency is desired, the conventional variable frequency dividing circuit drives the variable controller 20 to obtain a higher or lower frequency as desired.
As shown in FIG. 2, the variable controller 20 includes a decreasing controller 21, which outputs the decreasing control signal IN.sub.-- DEC in accordance with the frequency decreasing signal DECMT. The variable controller 20 also includes an increasing controller 31, which outputs the increasing control signal IN.sub.-- INC in accordance with the frequency increasing signal INCMT. Typically, the decreasing controller 21 includes a first flip-flop 22, which receives the frequency decreasing signal DECMT at its input terminal D and outputs a signal from its positive output terminal Q or negative output terminal Q according to the clock pulse CP. The decreasing controller 21 also includes a second flip-flop 23, which receives the positive output signal Q of the first flip-flop 22 at its input terminal D and outputs a signal from its positive output terminal Q according to the clock pulse CP. The decreasing controller 21 includes a first AND gate 25, which receives inputs from the negative output terminal Q of the first flip-flop 22 and the positive output terminal Q of the second flip-flop 23 to output the result of an AND operation to node N1. The decreasing controller 21 includes a second AND gate 24, which logically ANDs the signal at node N2 and a signal IN1. The decreasing controller 21 further includes a third flip-flop 26, which receives the output of the second AND gate 24 at its input terminal D, the output of the first AND gate 25 at its terminal TE, and the reset signal RST at its terminal T1 to output the signal to the node N2 through its positive output terminal Q according to the clock pulse CP. Finally, the decreasing controller 21 includes a fourth flip-flop 27, which receives the positive output signal Q of the third flip-flop 26 at its input terminal D, feeds the signal at its own positive output terminal Q back to its terminal T1, and receives signal IN1 at its terminal TE to output a signal at the positive output terminal Q to a node N3 and output the signal at the negative output terminal Q as the decreasing control signal IN.sub.-- DEC according to the clock pulse CP.
Also as shown in FIG. 2, the increasing controller 31 includes a fifth flip-flop 32, which receives the frequency increasing signal INCMT at its input terminal D and outputs a signal from its positive output terminal Q or negative output terminal Q according to the clock pulse CP. The increasing controller 31 also includes a sixth flip-flop 33, which receives the positive output Q of the fifth flip-flop 32 at its input terminal D and outputs a signal from its positive output terminal Q according to the clock pulse CP. The increasing controller 31 includes a third AND gate 35, which logically ANDs the negative output Q of the fifth flip-flop 32 and the positive output Q of the sixth flip-flop 33 to output the result of the AND operation to node N4. The increasing controller 31 includes a fourth AND gate 34, which logically ANDs the signal IN1 and the signal at node N5. A seventh flip-flop 36 receives the output of the fourth AND gate 34 at its input terminal D, the output of the third AND gate 35 at its terminal TE, and the reset signal RST at its terminal T1, and outputs its positive output Q to the node N5 according to the clock pulse CP. An eighth flip-flop 37 receives the positive output Q of the seventh flip-flop 36 at its input terminal D, its own positive output Q at its input terminal T1, and the signal IN1 at its terminal TE, and outputs its positive output signal Q to a node N6 according to the clock pulse CP. A ninth flip-flop 38 receives the positive output Q of the seventh flip-flop 37 at its input terminal D, feeds the signal at its positive output terminal Q back to its terminal T1, and receives the signal IN1 at its terminal TE to output its positive output Q to a node N7 according to the clock pulse CP. An OR gate 39 logically ORs the signal at the node N7 and the signal at the node N6, and outputs the ORed result as the increasing control signal IN.sub.-- INC.
As shown in FIG. 2, the clock pulse CP is inputted to the clock terminal CLK, of each of the first to ninth flip-flops 22, 23, 26, 27, 32, 33, 36, 37, 38. The reset signal RST is inputted to the clear terminal CLR of each of the nine flip-flops. If the reset signal RST is at a logical "low" level, all of the nine flip-flops are cleared. In contrast, if the reset signal RST is at a logical "high" level, all of the nine flip-flops operate according to the clock pulse CP.
As shown in FIG. 3, the frequency divider 40 includes a counting circuit 41, which divides the frequency of the clock pulse CP by four or by three. The frequency divider 40 also includes a counter controller 46, which controls the number of frequency divisions by four and the number of frequency divisions by three of the counting circuit 41 according to the output of the variable controller 20 to adjust a divided frequency.
The counting circuit 41 includes a first counter 42, which receives the reset signal RST at its terminals CD and T, a signal at node N12 at its terminal A, and the ground voltage at its terminal B. The first counter 42 generates an output CO to node N10. A first inverter 43 receives the output CO and feeds the inverted output to terminal L of the first counter 42. The first counter 42 outputs signals to nodes N8 and N9 through its output terminals QA and QB. The counting circuit 41 further includes a fifth AND gate 45, which logically ANDs the outputs QA and QB of the first counter 42, and outputs the ANDed result as a frequency-divided clock OUT-CLK.
The counter controller 46 includes a second counter 47, which receives the ground voltage at its terminal A, the clock pulse CP at its terminal CP, the output CO of the first counter 42 at its terminal T, and the reset signal RST at its terminal CD to generate an output signal at its terminal CO. The counter controller 46 also includes a sixth AND gate 49, which logically ANDs the output of the second counter 47 and the decreasing control signal IN.sub.-- DEC and outputs the ANDed result to the node N12. The output of the sixth AND gate 49 is a counter control signal. Further, the output from the terminal CO of the second counter 47 is inverted by a second inverter 48. The inverted output is then inputted to the variable controller 20 as the signal IN1 and to terminal L of the second counter 47.
In operation, the frequency decreasing signal DECMT and the frequency increasing signal INCMT of the variable controller 20 use a falling edge (from "1" to "0"). Generally, during normal operation, signals DECMT and INCMT have the binary value "1". When frequency variation is needed, they have the value "0". Under the above condition, each of nodes of the variable controller 20 has the following data values given by Table 1.
TABLE 1 __________________________________________________________________________ Division DECMT INCMT N1 N2 N3 N4 N5 N6 N7 IN.sub.-- INC IN.sub.-- DEC __________________________________________________________________________ Normal 1 1 0 0 0 0 0 0 0 0 1 Operation Frequency 1.fwdarw.0 1 1 1 0 0 0 0 0 0 Decrement Frequency 1 1.fwdarw.0 0 0 0 1 1 1 1 1 1 Increment __________________________________________________________________________
As shown in Table 1, the increasing control signal IN.sub.-- INC has the data "1" as an active value, and the decreasing control signal IN.sub.-- DEC has the data "0" as an active value.
In the frequency divider 40, the first counter 42 operates as a 2-bit clock and executes a counting operation up to data "11" from initial values A and B. Thus, the counter outputs the value of the terminal CO as the data "1". When a load signal L has the value of data "0", the first counter 42 loads the initial value, and when an operation signal T has the value of data "1", the counter executes the counting operation.
FIGS. 4A to 4I are waveform diagrams illustrating the operation at a normal state of FIG. 1.
FIG. 4A is a waveform of the clock pulse CP. FIG. 4B is a waveform of the reset signal RST. FIG. 4C is a waveform of the frequency decreasing signal DECMT. FIG. 4D is a waveform of the frequency increasing signal INCMT. FIG. 4E is a waveform of the signal at the node N1. FIG. 4F is a waveform of the signal at the node N4. FIG. 4G is a waveform of the signal at the node N8. FIG. 4H is a waveform of the signal at the node N9. FIG. 41 is a waveform of the frequency-divided output clock OUT.sub.-- CLK.
As shown in FIGS. 4A to 4I, at the normal state since the inputs A and B of the first counter 42 become data "00" and the input L, T and CD become data "1", the first counter 42 operates with the data values "00", "01", "10"and "11". While the first counter 42 is operating with the data value "11", whenever the output value at the total CO thereof is the data "1", the first counter 42 performs a frequency division by four by executing the counting operation at the data values "00", "01", "10" and "11". When the output value at the terminal CO of the second counter 47 is data "1", and AND gate 49 outputs the data "1" to the input A of the first counter 42. At the time, the first counter 42 performs a frequency division by three by executing the counting operation at the data values "01", "10" and "11". Thus, the output clock OUT.sub.-- CLK repeats the cycle in the order of a frequency division by four, a frequency division by four, a frequency division by four, and a frequency division by three (4-4-4-3).
FIGS. 5A to 5I are waveform diagrams illustrating the operation in a frequency decreasing state of FIG. 1.
FIG. 5A is a waveform of the clock pulse CP. FIG. 5B is a waveform of the reset signal RST. FIG. 5C is a waveform of the frequency decreasing signal DECMT. FIG. 5D is a waveform of the frequency increasing signal INCMT. FIG. 5E is a waveform of the signal on the node N1. FIG. 5F is a waveform of the signal on the node N4. FIG. 5G is a waveform of the signal on the node N8. FIG. 5H is a waveform of the signal on the node N9. FIG. 51 is a waveform of the frequency-divided output clock OUT.sub.-- CLK.
As shown in FIGS. 5A to 5I, if the frequency decreasing signal DECMT inputted to the variable controller 20 changes from a logical "high" to a logical "low" to decrease the frequency, a logical "high" pulse is generated at the node N1 to change the decreasing control signal IN.sub.-- DEC to the logical "low". As a result, the output clock OUT.sub.-- CLK repeats the cycle in the order of a frequency division by four, a frequency division by four, a frequency division by four, and a frequency division by four (4-4-4-4). Therefore, since the number of frequency division is increased in comparison with that in the normal state, the frequency of the output clock OUT.sub.-- CLK is decreased.
FIGS. 6A to 6I are waveform diagrams illustrating the operation in a frequency increasing state of FIG. 1.
FIG. 6A is a waveform of the clock pulse CP. FIG. 6B is a waveform of the reset signal RST. FIG. 6C is a waveform of the frequency decreasing signal DECMT. FIG. 6D is a waveform of the frequency increasing signal INCMT. FIG. 6E is a waveform of the signal on the node N1. FIG. 6F is a waveform of the signal on the node N4. FIG. 6G is a waveform of the signal on the node N8. FIG. 6H is a waveform of the signal on the node N9. FIG. 6I is a waveform of the frequency-divided output clock OUT.sub.-- CLK.
As shown in FIGS. 6A to 6I, if the frequency increasing signal INCMT inputted to the variable controller 20 changes from a logical "high" to a logical "low" to increase the frequency, a logical "high" pulse is generated at the node N4 to change the increasing control signal IN.sub.-- INC to the logical "high". Whenever the output value at the terminal CO thereof is the data "1", the second counter 47 executes the counting operation at the data values "10" and "11". Also, whenever the output value at the terminal CO of the second counter 47 is data "1", the AND gate 49 outputs the data "1" to the input A of the first counter 42. At the time, the first counter 42 performs the frequency division by three at data values "01", "10" and "11". Accordingly, the output clock OUT.sub.-- CLK repeats the cycle in the order of a frequency division by four, a frequency division by three, a frequency division by four, and a frequency division by four (4-3-4-3). Therefore, since the number of frequency division is decreased in comparison with that in the normal state, the frequency of the output clock OUT.sub.-- CLK is increased.
However, the conventional variable frequency dividing circuit has various problems. First, the construction of the variable controller constituting the variable non-integer times frequency dividing circuit is substantially complicated. Second, frequency increment and decrement according to the increasing and decreasing control signals occur after a long delay. Third, noise can not be avoided due to the use of falling edge of the frequency increasing signal INCMT and the frequency decreasing signal DECMT.